1. Technical Field
Various embodiments relate to a semiconductor circuit, and more particularly, to semiconductor integrated circuit.
2. Related Art
A semiconductor integrated circuit can be manufactured in a multi-channel structure having independent address/command and data buses in order to reduce random access time.
As shown in FIG. 1, a conventional semiconductor integrated circuit 1 may be configured to have two channels CH0 and CH1 as an example.
The two channels may be configured in the same manner.
The channel CH0 includes a plurality of memory blocks, e.g. a plurality of memory banks (hereinafter, referred to as “banks”) B0-B15, an input/output array 10, a command processing unit 30, a data bus 40, and a command bus 50.
The plurality of banks B0-B15 share the input/output array 10 with each other.
The command processing unit 30 controls the read/write operations with respect to the plurality of banks B0-B15 through the command bus 50 in response to an external command.
When a burst length is four (BL=4), in order to access mutually different banks in regular sequence in an operation of an access write/read precharge scheme, the conventional semiconductor integrated circuit 1 requires a timing margin of 3tCK so as to be accorded with a Row to Row Delay (tRRD) standard.
Therefore, as shown in FIG. 2, in order to output data of mutually different banks, a gap of 3tCK necessarily exists, thereby causing a loss of bandwidth.
In the conventional semiconductor integrated circuit 1, since the plurality of memory banks B0-B7 share the input/output array 10, as described above, input/output lines increase, and thus it is difficult to make an arrangement of the input/output lines.
In addition, on data output from mutually different banks, in order to be accorded with the tRRD standard, a timing margin is reduced and a loss of bandwidth is caused.